In the last decade, the increasing demand of electronic official and financial transactions, the use of digital signature applications and the requirements of information secrecy have made the random number generators (RNGs) more popular. With this respect, RNGs, which have been generally used for military cryptographic applications in the past, have now an important role in design of a typical digital communication equipment.
Almost all cryptographic systems require unpredictable values, therefore RNG is a fundamental component for cryptographic mechanisms. Generation of public/private key-pairs for asymmetric algorithms and keys for symmetric and hybrid crypto systems require random numbers. The one-time pad, challenges, nonces, padding bytes and blinding values are created by using truly random number generators (TRNGs). Pseudo-random number generators (PRNGs) generate bits in a deterministic manner. In order to appear to be generated by a TRNG, the pseudo-random sequences must be seeded from a shorter truly random sequence. RNGs are also used in many areas including Monte Carlo analysis, computer simulations, statistical sampling, stochastic optimization methods, watermarking for image authentication, authentication procedure between two crypto equipments and initial value randomization of a crypto module that realizes an algorithm.
Even if RNG design is known, any useful prediction about the output can not be made. To fulfill the requirements for secrecy of one-time pad, key generation and any other crypto-graphic applications, the TRNG must satisfy the following properties: The output bit stream of the TRNG must pass all the statistical tests of randomness; the next random bit must be unpredictable; the same output bit stream of the TRNG must not be able to reproduced. The best way to generate true random numbers is to exploit the natural randomness of the real world by finding a random event that happens regularly. Examples of such usable event include elapsed time during radioactive decay, thermal and shot noise, oscillator jitter and the amount of charge of a semiconductor capacitor.
There are few RNG designs reported in the literature; however fundamentally four different techniques were mentioned for generating random numbers: amplification of a noise source dual oscillator architecture, discrete-time chaotic maps and continuous-time chaotic oscillators. In spite of the fact that, the use of discrete-time chaotic maps in the realization of RNG is well-known for some time, it was only recently shown that continuous-time chaotic oscillators can be used to realize TRNGs also. Following up in this direction, we investigated the usefulness of the proposed innovation to generate random binary data from continuous-time chaotic oscillators with dual oscillator architecture.
The bit rates of RNGs commonly found in literature and commercial products became insufficient because of the increasing data rates of digital communication equipments. In comparison with RNGs based on discrete-time chaotic maps, amplification of a noise source and jittered oscillator sampling, it is seen that RNGs based on continuous-time chaotic oscillators can offer much higher and constant data rates without post-processing with less complex integrated circuits. In conclusion, we can deduce that continuous-time chaotic oscillators can be integrated on today's process at GHz range and the use of continuous-time chaos with the proposed innovation is very promising in generating random numbers with very high throughput.
In order to be compatible with other system elements, it is preferable to use chaotic oscillators that can be integrated on silicon. A number of attempts have been made to introduce discrete time as well as continuous-time CMOS chaotic oscillators. In most of these attempts, the resulting circuits were complicated and occupied a large silicon area. Discrete-time chaotic oscillators usually employ either switched-C or switched-current techniques. The utilization of a multiplier in addition to the many capacitors and op amps automatically result in a large circuit. In comparison with RNGs based on discrete-time chaotic sources it is seen that RNGs based on continuous-time chaotic sources can offer much higher data rates with less complex and less noisy integrated circuits, particularly due to the absence of successive sample-and-hold stages.
Amplification of a noise source technique shown in FIG. 1, uses a high-gain high-bandwidth amplifier to process the white noise which has small ac voltage. The noise must be amplified to a level where it can be accurately thresholded with no bias by a clocked comparator. This is the most popular RNG technique for single-chip or boardlevel solutions.
In low voltage CMOS integrated circuits, two different noise mechanisms generate wideband white noise: shot noise (generated by current flow across a p-n junction) and thermal noise (generated by random electron motion in a resistor). Avalanche noise is not a practical choice for a noise source because of the typical high breakdown voltage (>6V DC) of Lever diodes fabricated in bulk CMOS processes. As shown in FIG. 1, the integrated noise source topology uses a large resistor as a thermal noise generator. Resistors are easily fabricated from polysilicon or diffusion layers and require no bias current to generate noise, as semiconductor junctions do. A polysilicon resistor also has a low flicker noise index (typically −30 dB), ensuring low 1/f noise levels.
Assuming negligible 1/f noise, the thermal noise voltage of the source resistor RSTC will be Et=√{square root over (4kTRSTCΔf)} where k is Boltzmann's constant, T is absolute temperature, RSTC is the resistance, and Δf is the noise bandwidth. The noise bandwidth of Et is normally limited by the first-order low pass filter formed by RSTC and the equivalent amplifier input capacitance CAmp. Provided the −3 dB bandwidth of the amplifier is larger than the noise bandwidth, the total equivalent noise voltage Eni due to Et at the input of the amplifier will be
      E    ni    =            kT              C        Amp            where it is the theoretical limit for thermal noise generated by a resistor shunted with a capacitor. Thermal noise voltage amplitude over a 1 Hz bandwidth can be increased by increasing the value of RSTC, but at the cost of reduced thermal noise bandwidth, such that Eni will remain constant for a given CAmp.
The dual oscillator architecture uses a random source that is derived from two free-running oscillators, one fast and the other one slower as shown in FIG. 2. Published RNG designs using this technique report that typical levels of oscillator jitter are not nearly sufficient to produce statistical randomness. For this reason a noise source is used to modulate the frequency of the slower clock, and with the rising edge of the noise-modulated slower clock fast clock is sampled. Drift between the two clocks thus provides the source of random binary digits. Similarly to amplification of a noise source technique, the noise must be amplified to a level where it can be used to modulate the frequency of the slower clock. The slower clock frequency, which determines the throughput data rate, is basically limited by the bandwidth of the noise signal used for modulation where the main reason of the limitation is the bandwidth of the amplifier.